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ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 1 of 16 5c26 n - rev. f001 general description the ec 24c512 c are eeprom devices that use the industrial standard 2 - wire interface for communications. the ec 24c512 c contains a memory array of 512k - bits (65,536x8), which is organized in 128 - byte per page. the eeprom can ope rate in a wide voltage range from 1.7v to 5.5v w hich fits most application. this product can provide a low - power 2 - wire eeprom solution. the device is offered in lead - free, r ohs, halogen free or green. the available package type s are 8 - pin so p , tss op, dfn . the ec 24c512 c is compatible with the industrial standard 2 - wire bus protocol. if in case the bus is not responded, a new sent op - code command will reset the bus and the device will respond correctly. the simple bus consists of the serial clock wi re (scl) and the serial data wire (sda). utilizin g such bus protocol, a master device, such as a microcontroller, can usually control one or more slave devices, alike this ec24c512c. the bit stream over the sda line includes a series of bytes, whic h identifies a particular slave device, an instruction, an address within that slave device, and a series of data, if appropriate. the ec24c512c also has a write protect pin (wp) to allow blocking any write operations over specified memory area. the ec 2 4c512 c also offers an additional page, named the identification page (128 bytes) which can be written and (later) permanently locked in read - only mode. this identification page offers flexibility in the application board production line, as the identificat ion page can be used to store unique identification parameters and/or parameters specific to the production line. under no circumstance, the device will be hung up. in order to refrain the state machine entering into a wrong state during power - up sequence or a power toggle off - on condition, a power on reset circuit is embedded. during power - up, the device does not respond to any instructions until the supply voltage (vcc) has reached an acceptable stable level above the reset threshold voltage. once vcc pa sses the power on reset threshold, the device is reset and enters into the standby mode. this would also avoid any inadvertent write operations during power - up stage. during power - down process, the device will enter into standby mode, once vcc drops below the power on reset threshold voltage. in addition, the device will be in standby mode after receiving the stop command, provided that no internal write operation is in progress. nevertheless, it is illegal to send a command unless the vcc is within its operating level. features two - wire serial interface, i 2 c tm compatible C bi - directional data transfer protocol wide - voltage operation C v cc = 1.7v to 5.5v speed: 400 khz (1.7v) and 1 mhz (2.5v~5.5v) u a, 1.7v operating c urrent (max.): 0.5 ma, 1.7v hardware data protection C write protect pin sequential & random read features memory organization: 65,536 x 8 bits page size: 128 bytes page write mode C up to 128 bytes per page write - offer an 128 bytes additional page self timed write cycle with auto clear: 5ms (max.) filtered inputs for noise suppression high - reliability C endurance: 1 million cycles C data retention: 100 years industrial temperature grades packages: sop,tssop,dfn lead - free, rohs, hal ogen free, green
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 2 of 16 5c26 n - rev. f001 ordering information & marking information ec24c xxx c xx x x functional block diagram device function 512 512kbit (65536 8) r tape & reel t tube g green m1 sop 8l e1 tssop 8l f2 dfn 8l
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 3 of 16 5c26 n - rev. f001 pin no. pin name i/o definition 1 a0 i device address input 2 a1 i device address input 3 a2 i device address input 4 gnd - ground 5 sda i/o s erial address and data input and data out put 6 scl i serial clock input 7 wp i write protect input 8 v cc - power supply pin configuration ( sop 8l / tssop 8l ) (dfn 8l) pin definition pin descriptions scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi - directional pin used to transfer addresses and data into and out of the device. the sda pin is an open drain output and can be wired with other open drain or open collector outputs. however, the sda pin requir es a pull - up resistor connected to the power supply. a0, a1, a2 the a 0, a1 and a2 are the device address inputs. typically, the a0, a1, and a2 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. when a0, a1, and a2 are left floating, the inputs are defaulted to zero. wp wp is the write protect pin. while the wp pin is connected to the power supply of ec24c512c, the entire array becomes write protected (i.e. the device becomes read only). when wp is tied to ground or left floating, the normal write operations are allowed. vcc s upply voltage gnd ground of supply voltage
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 4 of 16 5c26 n - rev. f001 device operation the ec24c512c serial interface supports communications using industrial standard 2 - wire bus protocol, such as i 2 c . 2 - wire bus the two - wire bus is defined as serial data (sda), and serial clock ( scl). the protocol defines any device that sends data onto the sda bus as a transmitter, and the receiving devices as receivers. the bus is controlled by master device that generates the scl, controls the bus access, and generates the start and stop condit ions. the ec24c512c is the slave device. the bus protocol data transfer may be initiated only when the bus is not busy. during a data transfer, the sda line must remain stable whenever the scl line is high. any changes in the sda line while the scl line i s high will be interpreted as a start or stop condition. the state of the sda line represents valid data after a start condition. the sda line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed d uring the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated by a stop condition. start condition the start condition precedes all commands to the device and is d efined as a high to low transition of sda when scl is high. the eeprom monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defined as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge after a successful data transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the ec24c512c contains a reset function in case th e 2 - wire bus transmission on is accidentally interrupted (e.g. a power loss), or needs to be terminated mid - stream. the reset is initiated when the master device creates a start condition. to do this, it may be necessary for the master device to monitor th e sda line while cycling the scl up to nine times.(for each clock signal transition to high, the master checks for a high level on sda.) standby mode while in standby mode, the power consumption is minimal. the ec24c512c enters into standby mode during on e of the following conditions: a) after power - up, while no op - code is sent; b) after the completion of an operation and followed by the stop signal, provided that the previous operation is not write related; or c) after the completion of any internal write operations. device addressing the master begins a transmission on by sending a start condition, then sends the address of the particular slave devices to be communicated. the slave device address is 8 bi ts format as shown in figure. 5. the four most sign ificant bits of the slave address are fixed (1010) for ec24c512c . the next three bits, a0, a1 and a2, of the slave address are specifically related to eeprom. up to eight ec24c512c units can be connected to the 2 - wire bus. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, read operation is selected. while it is set to 0, write operation is selected. after the master transmits the start condition and slave address byte appropriately, the associated 2 - wire slave device, ec24c512c , will respond with ack on the sda line. then ec24c512c will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the ec24c512c th en prepares for a read or write operatio n by monitoring the bus.
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 5 of 16 5c26 n - rev. f001 write operation byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/w set to zero) to the slave device. after the slave generates an ack, the master sends the byte address that is to be written into the address pointer of the ec24c512c . after receiving another ack from the slave, the master device transmits the data byte to be written into the address memory location. the ec24c512c acknowledges once more an d the master generates the stop condition, at which time the device begins its internal programming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the ec24c512c is capable of 128 - byte page - write operation. a page - write is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transferred, the master device can transmit up to 127 more bytes. after the receip t of each data word, the eeprom responds immediately with an ack on sda line, and the seven lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. if a byte address is inc remented from the last byte of a page, it returns to the first byte of that page. if the master device should transmit more than 128 bytes prior to issuing the stop condition, the address counter will roll over, and the previously written data will be ov erwritten. once all 128 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the ec24c512c in a single write cycle . all inputs are disabled until comple tion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the ec24c512c initi ates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the eeprom is still busy with the write operation, no ack will be returned. if the ec 24c512c has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write identification page the identification page(128 byte s) i s an additional page which can be written and (later) pe rmanently locked in read - only mode. it is written by issuing the write identification page instruction. this instruction uses the same protocol and format as page write (into memory array), except for the following differences: device type identifier=1011 b msb address bits a15/a7 are dont care except for address bit a10 which must be 0. lsb address bits a6/a0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during t he write identification page instruction are not acknowledged (noack). lock identification page the lock identification page instruction (lock id) permanently locks the identification page in read - only mode. the lock id instruction is similar to byte writ e (into memory array) with the following specific condition: device type identifier=1011b address bit a10 must be 1; all other address bits are dont care the data byte must be equal to the binary value xxxx xx1x, where x is dont care
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 6 of 16 5c26 n - rev. f001 read operati on read operation read operations are initiated in the same manner as write operations, except that the (r/w) bit of the slave address is set to 1. there are three read operation options: current address read, random address read and sequential read. cu rrent address read the ec24c512c contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. when the eeprom receives the slave addressing byte with a read operation (r/w bit set to 1), it will respond an ack and transmit the 8 - bit data byte stored at address location n+1. th e master should not acknowledge the transfer but should generate a stop condition so the ec24c512c discontinues transmission. if 'n' is the last byte of the memory, the data from location '0' will be transmitted. (refer to figure 8. current address read di agram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a 'dummy' write operation by sending the start condition, slave address and byte a ddress of the location it wishes to read. after the ec24c512c acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/w bit set to one. the eeprom then responds with its ack and sends the dat a requested. the master device does not send an ack but will generate a stop condition. (refer to figure 9. random address read diagram.) sequential read sequential reads can be initiated as either a current address read or random address read. after the ec24c512c sends the initial byte sequence, the master device now responds with an ack indicating it requires additional data from the ec24c512c. the eeprom continues to output data for each ack received. the master device terminates the sequential read ope ration by pulling sda high (no ack) indicating the last data word to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. the address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operation. when the memory address boundary of the array is reached, the address counter rolls over to address 0, and the device continues to output data. (ref er to figure 10. sequential read diagram). read identification page the identification page can be read by issuing an read identification page instruction. this instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b.the msb address bits a15/a7 are dont care, the lsb address bits a6/a0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g.:when reading the id entification page from location 100d, the number of bytes should be less than or equal to 28, as the id page boundary is 128 bytes). read the lock status the locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page is unlocked, otherwise a noack bit if the identification page is locked. right after this, it is recomm ended to transmit to the device a start followed by a stop condition, so t hat: start: the truncated command is not executed because the start condition resets the device internal logic. stop: the device is the n set back into standby mode by the stop condition.
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 7 of 16 5c26 n - rev. f001 diagrams figure 1. typical system bus configuration figure 2. output acknowledge figure 3. start and stop conditions figure 4. data validity protocol ec24c512c
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 8 of 16 5c26 n - rev. f001 figure 5. slave address figure 6. byte write figure 7. page write f igure 8. current address read
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 9 of 16 5c26 n - rev. f001 figure 9. random address read figure 10. sequential read
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 10 of 16 5c26 n - rev. f001 timing diagrams figure 11 .bus timing figure 12. write cycle timing
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 11 of 16 5c26 n - rev. f001 symbol parameter value unit v s supply voltage - 0.5 to + 6.5 v v p voltage on any pin C 0.5 to vcc + 0.5 v t bias temper ature under bias C 55 to +125 c t stg storage temperature C 65 to +150 c i out output current 5 ma range ambient temperature (t a ) v cc industrial C 40c to +85c 1.7v to 5.5v symbol parameter [1,2] conditions max. unit c in input capacitance v in = 0v 6 pf c i/o input / output capacitance v i/o = 0v 8 pf electrical characteristics absolute maximum ratings note: stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not implied. exposure to absolut e maximum rating conditions for extended periods may affect reliability. operating range capacitance note : (1) tested initially and after any design or process changes that may affect these parameters and not 100% tested. (2) test conditions: t a = 25c, f = 1 mhz, v cc = 5.0v.
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 12 of 16 5c26 n - rev. f001 symbol parameter [1] v cc test conditions min. typ . max. unit v cc supply voltage 1.7 -- 5.5 v v ih input high voltage 0.7*vcc -- v cc +1 v v il input low voltage - 1 -- 0.3* v cc v i li input leakage cu rrent 5v v in = v cc max -- -- 2 a i lo output leakage current 5v -- -- 2 a v ol1 output low voltage 1.7v i ol = 0.15 ma -- 0.2 v v ol2 output low voltage 3v i ol = 2.1 ma -- 0.4 v i sb1 standby current 1.7v v in = v cc or gnd 0.2 1 a i sb2 standby current 2.5v v in = v cc or gnd 0. 3 1 a i sb3 standby current 5v v in = v cc or gnd 0.5 1 a i cc1 read current 1.7v read at 400 khz 0. 1 5 ma icc1 read current 2.5v read at 1 mhz 0.2 ma icc1 read current 5.5v read at 1 mhz 0.5 ma i cc2 write current 1.7v write at 400 khz 0.5 ma icc2 write current 2.5v write at 1 mhz 0.6 ma icc2 write current 5.5v write at 1 mhz 1 ma dc electrical characteristic industrial: t a = C 40c to +85c, v cc = 1.7v ~ 5.5v note: the parameters are characterized but not 100% tested.
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 13 of 16 5c26 n - rev. f001 symbol parameter [1][2] 1.7v v cc <2.5v 2.5v v cc <4.5v 4.5v v cc 5.5v unit min. max. min. max. min. max. unit f scl sck clock frequency 400 1000 1000 khz t low clock low period 1200 400 400 ns t high clock high period 600 400 400 ns t r rise time (scl and sda) 300 300 300 ns t f fall time (scl and sda) 300 100 100 ns t su:sta start condition setup time 600 200 200 ns t su:sto stop condition setup time 600 200 200 ns t hd:sta start condition hold time 600 200 200 ns t su:dat data in setup time 100 40 40 ns t hd:dat data in hold time 0 0 0 ns t aa clock to output access time (scl low to sda data out valid) 100 900 50 400 50 400 ns t dh data out hold time (scl low to sda data out change) 100 50 50 ns t wr write cycle time 5 5 5 ms t buf bus free time before new transmission 1000 400 400 ns t su:wp wp pin setup time 600 400 400 ns t hd:wp wp pin hold time 1200 1200 1200 ns t noise suppression time 100 50 50 ns ac electrical characteristic industrial: t a = C 40c to +85c, supply voltage = 1.7v to 5.5v note: (1) the parameters are characterized but not 100% tested. (2) ac measurement conditions: r l (connects to v cc ): 1.3 k? (2.5v, 5.0v), 10 k? (1.7v) c l = 100 pf input pulse voltages: 0.3*v cc to 0.7*v cc input rise and fall times: 50 ns timing reference voltages: h alf v cc level
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 14 of 16 5c26 n - rev. f001 package information sop 8l note: 1. controlling dimension: mm 2. di mension d and e1 do not include mold protrusion 3. dimension b does not include dambar protrusion/intrusion. 4. refer to jedec standard ms - 012 5. drawing is not to scale symbols dimensions in millimeters dimensions in inches min nom max min nom max a 1.35 -- 1.75 0.053 -- 0.069 a1 0.10 -- 0.25 0.004 -- 0.010 b 0.33 -- 0.51 0.013 -- 0.020 d 4.80 -- 5.00 0.189 -- 0.197 e 5.80 -- 6.20 0.228 -- 0.244 e1 3.80 -- 4.00 0.150 -- 0.157 e 1.27 bsc. 0.050 bsc. l 0.38 -- 1.27 0.015 0.050 l1 0.25 bsc. 0.010 bsc. zd 0.545 ref. 0.021 ref. 0 -- 8 0 -- 8
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 15 of 16 5c26 n - rev. f001 ts sop 8l note: 1. controlling dimension: mm 2. dimension d and e do not include mold protrusion 3. dimension b does not include dambar protrusion/intrusion. 4. refer to jedec standard mo - 153 aa 5. drawing is not to scale 6. package may have exposed tie bar. s ymbols dimensions in millimeters dimensions in inches min nom max min nom max a -- -- 1.20 -- -- 0.047 a1 0.05 -- 0.15 0.002 -- 0.006 a2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 -- 0.30 0.007 -- 0.012 c 0.09 -- 0.20 0.004 -- 0.008 d 2.90 3.00 3.10 0 .114 0.118 0.122 e 4.30 4.40 4.50 0.169 0.173 0.177 e1 6.4 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 0 -- 8 0 -- 8
ec24c512c 512k bits two - w ire serial eeprom e - cmos corp. ( www.ecmos.com.tw ) page 16 of 16 5c26 n - rev. f001 dfn 8l note: 1. controlling dimension: mm 2. drawing is not to scale symbols dimensions in millimeters dimensions in inches min nom max min nom max a 0.50 0.55 0.60 0.020 0.022 0.024 a1 0.00 -- 0.05 0.000 -- 0.002 b 0.18 0.25 0.30 0.007 0.010 0.012 a2 0.152 ref 0.006 ref d 2.00 b sc 0.079 bsc d2 1.25 1.40 1.50 0.049 0.055 0.059 e 3.00 bsc 0.118 bsc e2 1.15 1.30 1.40 0.045 0.051 0.055 e 0.50 bsc. 0.020 bsc. k 0.40 -- -- 0.016 -- -- l 0.20 0.30 0.40 0.008 0.012 0.016

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